sl74HC573 system logic semiconductor sls octal 3 - state noninverting transparent latch high - performance silicon - gate cmos the sl 74HC573 is identical in pinout to the ls/als573. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with ls/alsttl outputs. these latches appear transparent to data (i.e., the outputs change asynchronously) when latch enable is high. when latch enable goes low, data meeting the setup and hold time becomes latched. outputs directly interface to cmos, nmos, and ttl operating voltage range: 2.0 to 6.0 v low input current: 1.0 m a high noise immunity characteristic of cmos devices ordering information sl 74HC573n plastic sl 74HC573d soic t a = - 55 to 125 c for all packages function table inputs output output enable latch enable d q l h h h l h l l l l x no change h x x z x = don?t care z = high impedance logic diagram pin 20=v cc pin 10 = gnd pin assignment
sl 74HC573 system lo gic semiconductor sls maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) - 0.5 to +7.0 v v in dc input voltage (referenced to gnd) - 1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) - 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 35 ma i cc dc supply cur rent, v cc and gnd pins 75 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature - 65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soi c package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 m w/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types - 55 +125 c t r , t f input rise and fall time (figure 1) v cc =2.0 v v cc =4.5 v v cc =6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions mus t be taken to avoid applications of any voltage higher than maximum rated voltages to this high - impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropri ate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
sl74HC573 system logic semiconductor sls dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to - 55 c 85 c 125 c unit v ih minimum hi gh - level input voltage v out =0.1 v or v cc - 0.1 v i out 20 m a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il maximum low - level input voltage v out =0.1 v or v cc - 0.1 v i out 20 m a 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 v v oh minimum high - level output voltage v in =v ih or v il i out 20 m a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il i out 6.0 ma i out 7.8 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low - level output voltage v in = v il or v ih i out 20 m a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v il or v ih i out 6.0 ma i out 7.8 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current v in =v cc or gnd 6.0 0.1 1.0 1.0 m a i oz maximum three state leak age current output in high - impedance state v in =v ih or v il v out = v cc or gnd 6.0 0.5 5.0 10 m a i cc maximum quiescent supply current (per package) v in =v cc or gnd i out =0 m a 6.0 4.0 40 160 m a
sl 74HC573 system lo gic semiconductor sls ac electrical characteristics (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to - 55 c 85 c 125 c unit t plh , t phl maximum propagation delay, input d to q (figures 1 and 5) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns t plh , t phl maximum propagation delay,latch enable to q (figures 2 and 5) 2.0 4.5 6.0 160 32 27 200 40 34 240 48 41 ns t plz , t phz maximum propagation delay, output enable to q (figures 3 and 6) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns t pzh , t pzl maximum propagation delay, output enable to q (figures 3 and 6) 2.0 4 .5 6.0 150 30 26 190 38 33 225 45 38 ns t tlh , t thl maximum output transition time, any output (figures 1 and 5) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns c in maximum input capacitance - 10 10 10 pf c out maximum three - state output capacitance (output in high - impedance state) - 15 15 15 pf power dissipation capacitance (per enabled output) typical @25 c,v cc =5.0 v c pd used to determine the no - load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc 23 pf timing requirements (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to - 55 c 85 c 125 c unit t su minimum setup time, input d to latch enable (figure 4) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns t h minimum hold time, latch enable to input d (figure 4) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns t w minimum pulse width, latch enable (figure 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns t r, t f maximum input rise and fall times (figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns
sl74HC573 system logic semiconductor sls figure 1. switching waveforms figure 2. switching waveforms figure 3. switching waveforms figure 4. switching waveforms figure 5. test circuit figure 6. test circuit expanded logic diagram
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